U
UNIVEXA
ENGINEERING TOOLS / PROTOCOL LAB
● SIMULATOR READY
Embedded systems · Lab 01

I²C Protocol Lab

Inspect a randomly generated 7-bit slave address and its reference SDA/SCL transaction. Then recreate the bus sequence with five software-I²C commands and compare your waveform to the reference.

OPEN-DRAINLOGIC HIGH = RELEASE
01 / Reference transaction
GENERATED SIGNAL
7-bit slave address0x52
R/W bitW · 0
Expected ACKACK · 0
REFERENCE / IDEAL LOGIC TRACESTART / 9 CLOCKS / STOP
SDA · DATASCL · CLOCKTIME →
02 / Recreate the transaction
YOUR SIGNAL VS REFERENCE
Build the bus sequence

Use the five buttons to insert commands, or type directly. Create START, the 8 address/RW bits, ACK on clock 9, and STOP. Each delay holds the current line state for one sample.

Insert command

user_sequence.i2cONE COMMAND PER LINE
0 commandsHIGH = RELEASE
03 / Waveform comparison
USER RECONSTRUCTION
YOUR SDA / SCL OUTPUTNOT RUN
SDA · YOUR OUTPUTSCL · YOUR OUTPUT
REFERENCE SDA / SCLEXPECTED
Run report
VALIDATION
EVENT LOG
Simulator initialized · awaiting sequence